1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a semiconductor memory apparatus that is capable of reducing ground noise and reducing power consumption.
2. Related Art
As design technology and process technology of semiconductor memory apparatuses have been developed, a degree of integration thereof has been increased. As a result, semiconductor memory apparatuses that can operate with a low operation voltage have been developed. As such, with an increase in an integration density of the semiconductor memory apparatuses, a design rule of a unit cell that is smaller than a sub-micron unit is used in designing memory apparatuses. As a result, various elements that form the memory circuits have been reduced in size. Meanwhile, a system adapted for the semiconductor memory apparatuses is designed such that as a frequency of a central processing unit (CPU) increases, the semiconductor memory apparatuses can also operate with a high frequency. As a result, while the various elements have been reduced in size, in order to design memory circuits in which a high frequency operation can be performed, a decrease in a power supply voltage VDD is inevitable. For example, in a semiconductor memory apparatus, such as a synchronous DRAM having a level higher than a DDR3, which has attracted attention as the next generation of memory, a power supply voltage of 1.5 V or less is required. In particular, for example as for a DRAM that is mounted on a portable electronic devices and/or communication apparatus, recent research has progressed where an operation voltage is in a range of 1.0 V or less.
Even though the semiconductor memory apparatus strives to achieve a high frequency operation, a high integration degree and low power consumption, it is important to efficiently resolve problems, such as current consumption and noise inside a chip. In particular, it is important to reduce a ground bouncing noise occurring among banks, and an operation current and a leak current of the banks, because these are associated with operational stability of the semiconductor memory apparatus.
FIG. 1 is a simplified block diagram illustrating a ground power supply connection structure of a general bank. In general, the semiconductor memory apparatus includes a plurality of banks, each of which has the same structure as that shown in FIG. 1. According to an inner structure of the bank, the bank includes a core block 100 that has a memory cell array and a bit line sense amplifier array, a row control block 200 (X control block) that drives a row address signal of the core block 100, a column control block 300 (Y control block) that drives a column address signal of the core block 100, and a bank internal control block 400 (XY control block) that controls the row control block 200 and the column control block 300 according to a bank selection command.
In particular, in a connection structure shown in FIG. 1, a ground power supply pad 10 (VSS PAD) is disposed outside the bank, and the row control block 200, the column control block 300, and the bank internal control block 400 are connected in common to the ground power supply pad 10. In addition, the core block 100 is directly connected to a node “A” so as to protect regions of memory cells (not shown) from noise of the other blocks.
FIG. 2 is a block diagram specifically illustrating a ground power supply connection structure inside the core block 100 of FIG. 1. The core block 100 includes a cell array 110 where a plurality of memory cells are disposed, a bit line sense amplifier array 120 (BLSA array) where a plurality of sense amplifiers, each sensing data of each of the memory cells, are disposed, a sub word line driver array 130 (SWL driver array) that drives word lines of the memory cells, and a sub hole 140 where a relay is disposed to relay a bit line dividing signal and a bit line equalizing signal. FIG. 2 shows a case in which a semiconductor memory apparatus uses a sub word line scheme.
In the structure of FIG. 2, the bit line sense amplifier array 120, the sub word line driver array 130, and the sub hole 140 are connected in common to one ground line VSS.
Meanwhile, as a capacitance of a semiconductor memory apparatus is increased, the number of memory cells in the core block 100 is increased. Thus the number of each of the bit line sense amplifiers and the sub word line drivers is increased. In addition, sizes of the row control block 200 and the column control block 300 that control the core block 100, and a size of the bank internal control block 400 are also increased. If the bank 100 performs an activation operation, a large number of transistors in the core block 100 are driven, which causes ground noise. Therefore, in order to minimize an influence on the other blocks in the same bank, that is, the row control block 200, the column control block 300, and the bank internal control block 400 due to the ground noise, a ground source is connected to the node A, as shown in FIG. 1. However, as the capacitance of the semiconductor memory apparatus is increased, a ground noise due to an activation operation of the selected bank is gradually increased. Also, even when the bank is not selected, an amount of leak current of the respective control blocks in the bank is also increased. The leak current is increased when the capacitance of the semiconductor memory apparatus is increased.